123 lines
6.0 KiB
Markdown
123 lines
6.0 KiB
Markdown
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title = "LC-2"
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weight = 100
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LC-2 is the first architecture in the Little Computer family that looks like a
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real ISA. Built as a successor to the minimalist LC-1,[^lc1-successor] it
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introduced eight general-purpose registers and a three-state condition code
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system, the foundation that every subsequent architecture in the family would
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inherit.[^lc-family-evolution]
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[^lc1-successor]: {{< cite-ics edition="1" chapter="1. Welcome Aboard" page="2" >}}
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[^lc-family-evolution]: {{< cite-talk
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author="Patt, Yale N."
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title="LC-3, x86, or MIPS: The First ISA for Students to Study"
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type="Keynote"
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event="Workshop on Computer Architecture Education"
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location="San Diego, CA"
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date="June 9, 2007"
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url="https://www.csc2.ncsu.edu/faculty/efg/wcae/ISCA2007/FinalProgram.html"
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format="PowerPoint presentation"
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accessed="June 8, 2026"
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url-archived="https://web.archive.org/web/20250129103001/https://www.csc2.ncsu.edu/faculty/efg/wcae/ISCA2007/FinalProgram.html"
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url-archived-date="January 29, 2025"
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>}}
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LC-2 operates on a 16-bit data bus and a 16-bit address bus, giving a linear
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address space of 65,536 word-sized locations, 128 KiB of addressable memory in
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total. Every instruction is exactly 16 bits wide, with the top 4 bits reserved
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for the opcode. This fixed encoding means that the opcode, operands, and any
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immediate values must all fit within those 16 bits, a constraint that shapes the
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design of every instruction in the set.[^lc2-overview]
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[^lc2-overview]: {{< cite-ics edition="1" chapter="Appendix A: The LC-2 ISA" page="429" >}}
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## Registers
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LC-2 has a small but complete set of registers. All registers are 16 bits wide,
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matching the data bus width of the architecture.
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### General-Purpose Registers
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LC-2 provides eight general-purpose registers, named R0 through R7. They are
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symmetric: no register has a special hardware role, and any of them can be used
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as a source or destination in any instruction that operates on
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registers.[^lc2-overview] That said, two registers have a conventional role: R6
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is typically used as the stack pointer,[^lc2-stack] [^lc2-rti] and R7 is used
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by some instructions to store the return address.[^lc2-jsr-jsrr] [^lc2-ret]
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[^lc2-trap] See the [instructions page](instructions/) for details.
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[^lc2-stack]: {{< cite-ics edition="1" chapter="10.1.3 Implementation in Memory" page="197" page-end="200" >}}
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[^lc2-rti]: {{< cite-ics edition="1" chapter="Appendix A.3 The Instruction Set" page="444" >}}
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[^lc2-jsr-jsrr]: {{< cite-ics edition="1" chapter="Appendix A.3 The Instruction Set" page="436" page-end="437" >}}
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[^lc2-ret]: {{< cite-ics edition="1" chapter="Appendix A.3 The Instruction Set" page="443" >}}
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[^lc2-trap]: {{< cite-ics edition="1" chapter="Appendix A.3 The Instruction Set" page="448" >}}
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### Special-Purpose Registers
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Beyond the general-purpose registers, LC-2 has some special-purpose registers
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that control the execution of the processor. None of these registers are
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directly accessible from assembly, with the exception of the CC, which is
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implicitly read by conditional branch instructions.
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* The **Program Counter** (**PC**) holds the address of the next instruction to
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be fetched from memory. It is incremented by 1 after each fetch, before the
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instruction is executed, so that by the time the instruction runs, the PC
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already points to the following one.[^lc2-fetch]
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[^lc2-fetch]: {{< cite-ics edition="1" chapter="4.2.2 The Instruction Cycle" page="82" page-end="83" >}}
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* The **Instruction Register** (**IR**) holds the instruction currently being
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executed. After the PC is used to fetch an instruction from memory, the
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instruction is loaded into the IR, where it remains for the duration of the
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decode and execute phases.[^lc2-fetch]
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* The **Memory Address Register** (**MAR**) holds the address of the memory
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location to be accessed. Before any memory operation, the address is loaded
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into the MAR, which then drives the address bus during the read or write
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cycle.[^lc2-memory]
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[^lc2-memory]: {{< cite-ics edition="1" chapter="4.1.1 Memory" page="75" page-end="77" >}}
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* The **Memory Data Register** (**MDR**) holds the data being transferred to or
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from memory. On a read, the MDR receives the value fetched from the location
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addressed by the MAR. On a write, the MDR holds the value to be stored before
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it is placed onto the data bus.[^lc2-memory]
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* The **Condition Code** register (**CC**) is a 3-bit register that tracks the
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sign of the last value written to any general-purpose register. It has three
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mutually exclusive states: N (negative), Z (zero), and P (positive). Exactly
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one of the three bits is set at any given time.[^lc2-overview]
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Not all instructions update the CC. Only instructions that write a value to a
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general-purpose register will modify it. As an example, an `ADD` instruction
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that stores its result in R0 will update the CC based on the sign of that
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result, while a `STR` instruction that writes to memory will
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not.[^lc2-condition-codes]
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[^lc2-condition-codes]: {{< cite-ics edition="1" chapter="5.1.7 Condition Codes" page="95" >}}
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## Startup Behavior
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The ISA does not specify a default starting address or reset vector. Where the
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PC is initialized when the processor powers on or resets is left entirely to
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the implementation. {{< citation-needed >}}
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## Interrupt Support
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LC-2 provides support for vectored interrupts. When an interrupt is serviced,
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the processor pushes the current PC and CC onto the stack, then reads an 8-bit
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value from the interrupting device, called the interrupt vector (`INTV`).
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`INTV` is zero-extended to 16 bits and used as a memory address into the
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interrupt table: the value stored at that address is loaded into the PC,
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transferring control to the interrupt handler.{{< citation-needed >}}
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The `RTI` (Return from Interrupt) instruction reverses this process, popping
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the PC and CC from the stack to resume the interrupted
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program.{{< citation-needed >}}
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Beyond this, the ISA does not specify the interrupt protocol in further detail:
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the bus signaling and acknowledgment mechanism used to deliver `INTV` are left
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to the implementation.
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