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6.2 KiB
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142 lines
6.2 KiB
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title = "ISA Documentation"
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comments = false
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cascade.type = "docs"
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The best way to understand a CPU is to take one apart. The Little Computer
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family was designed with exactly that in mind: every detail is intentional,
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every constraint has a reason. The three canonical architectures (LC-2, LC-3,
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and LC-3b) were built to be studied, not just used, and their internal structure
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reflects that philosophy at every level.
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At the core, all three share the same foundation. The address bus is 16 bits
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wide, giving a linear address space of 65,536 locations, no segmentation, no
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paging, no virtual memory. Each architecture uses eight general-purpose
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registers (R0-R7), a program counter (PC), and a 3-bit condition code register
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(CC) that tracks the sign of the last result written to a register: negative,
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zero, or positive. Every instruction is exactly 16 bits wide, with the top 4
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bits reserved for the opcode, a constraint that shapes the design of every
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instruction in the set.
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Each successive version refines this foundation rather than replacing it. LC-2
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and LC-3 pair the 16-bit address bus with a 16-bit data bus, meaning each memory
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location holds a full 16-bit word - 128 KiB of addressable memory in total.
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LC-3b narrows the data bus to 8 bits: memory locations hold a single byte,
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halving the addressable memory to 64 KiB and introducing byte-level memory
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operations absent in the other two. LC-3 and LC-3b also add privilege levels - a
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distinction between user mode and supervisor mode - which the original LC-2 does
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not have.
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What none of them have is equally telling: no flags register, no status
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register, no variable-length instructions, no complex addressing hierarchies.
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The simplicity is not a limitation, it is the point.
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Beyond the canonical three, two other architectures are documented here. LC-1
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predates LC-2 and represents the earliest iteration of the family: simpler, more
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constrained, and rarely discussed today. LC-3.2 sits at the other end: an
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unofficial extension that expands the address space to 32 bits and reduces the
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word size to 8 bits, bringing the family closer to the real-world architectures
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it was never meant to replicate.
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## How the Family Evolved
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{{% steps %}}
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### LC-1
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The starting point of the family. An accumulator-based architecture with a
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single register, a 13-bit address space, and just 8 instructions. Extremely
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minimal by design. Closer to a teaching toy than a real CPU.
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### LC-2
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LC-2 marks the transition from a single-accumulator model to a proper register
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file. The initial revision introduced 4 registers and N,Z condition codes. This
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is a first step away from the extreme minimalism of LC-1.
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The final revision settled on 8 registers (R0-R7) and three condition codes (N,
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Z, P), the blueprint that all subsequent canonical architectures would inherit.
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The result is an architecture that feels closer to early 8-bit CPUs like the
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Intel 8080: still simple, but no longer a toy.
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### LC-3
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The most widely known architecture in the family. The initial revision
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introduced a stack that grows toward zero, PC-relative offsets using sign
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extension instead of zero extension, and register-relative addressing with
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signed offsets.
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The revised version added privileged memory, available in two models: fixed and
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selectable. LC-3 has been adopted by numerous universities as the basis for
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introductory computer architecture courses.
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### LC-3b
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A variant of LC-3 with an 8-bit data bus instead of 16-bit, halving the
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addressable memory to 64 KiB but introducing byte-level memory operations.
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Working at the byte level makes LC-3b the closest of the canonical architectures
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to how real-world CPUs actually handle memory.
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### LC-3.2
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An unofficial extension, not created by Patt and Patel, that expands the address
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bus to 32 bits and narrows the data bus to 8 bits - the same combination used by
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early x86 processors. It is the only architecture in the family that bridges the
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gap between the LC teaching model and real-world CPU design, which is what makes
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it worth studying.
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{{% /steps %}}
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## At a Glance
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| ISA | Data Bus Width | Address Bus Width | Memory | Registers | Instruction Width | Privilege Levels | Status |
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|:------:|:--------------:|:-----------------:|:-------:|:----------------------------------:|:-------------------------:|:----------------:|:-----------:|
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| LC-1 | 16-bit | **13-bit** | 16 kiB | **One 16-bit accumulator** | 16-bit (**3-bit** opcode) | No | **Legacy** |
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| LC-2 | 16-bit | 16-bit | 128 kiB | Eight 16-bit registers (R0-R7) | 16-bit (4-bit opcode) | No | Canonical |
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| LC-3 | 16-bit | 16-bit | 128 kiB | Eight 16-bit registers (R0-R7) | 16-bit (4-bit opcode) | Yes (2) | Canonical |
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| LC-3b | **8-bit** | 16-bit | 64 kiB | Eight 16-bit registers (R0-R7) | 16-bit (4-bit opcode) | Yes (2) | Canonical |
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| LC-3.2 | **8-bit** | **32-bit** | 4 GiB | **Eight 32-bit registers** (R0-R7) | 16-bit (4-bit opcode) | Yes (2) | **Variant** |
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## A Note on Sources
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All data in this section is sourced from primary references: the original books,
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course materials, and official publications by Patt and Patel. Every claim is
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cited. If you spot an error or know of a better source, contributions are
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[welcome via GitHub](https://github.com/little-emulator/docs/issues).
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## Explore the Architectures
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Each architecture in the family has its own dedicated reference page,
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documenting the instruction set, registers, memory model, and encoding in full
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detail.
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### Core Architectures
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<br>
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{{< hextra/feature-grid cols="2" >}}
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{{< hextra/feature-card title="LC-2" icon="chip" link="lc-2" >}}
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{{< hextra/feature-card title="LC-3" icon="chip" link="lc-3" >}}
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{{< hextra/feature-card title="LC-3b" icon="chip" link="lc-3b" >}}
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{{< /hextra/feature-grid >}}
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### Beyond the Canon
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<br>
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{{< hextra/feature-grid cols="2" >}}
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{{< hextra/feature-card title="LC-1" icon="bookmark" link="lc-1" subtitle="**Legacy**: The accumulator-based predecessor" >}}
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{{< hextra/feature-card title="LC-3.2" icon="cube" link="lc-3.2" subtitle="**Variant**: An unofficial 32-bit extension" >}}
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{{< /hextra/feature-grid >}}
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