82 lines
4.9 KiB
Markdown
82 lines
4.9 KiB
Markdown
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title = "Memory"
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weight = 110
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LC-2 has a 16-bit address bus, giving a linear address space of 65,536
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locations, numbered from `0x0000` to `0xFFFF`. Memory is canonically divided
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into 2<sup>7</sup> pages of 2<sup>9</sup> words each. There is no segmentation,
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no paging, and no virtual memory: every address maps directly to a physical
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location.[^lc2-overview]
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[^lc2-overview]: {{< cite-ics edition="1" chapter="Appendix A: The LC-2 ISA" page="429" >}}
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Addressability is 16 bits: each location in memory holds exactly one word,
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matching the width of the data bus. A single memory access always transfers a
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full 16-bit value, never a partial word, which is also why the concept of
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endianness does not apply here: there is no multi-byte value to order within a
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single access.
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## Memory Map
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The memory map below reflects the conventions of the standard LC-2 operating
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system, not the ISA itself. The ISA only defines the trap vector table at
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`0x0000 - 0x00FF`. Everything else, from the location of the OS to the boundary
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of userspace, is a software convention rather than a hardware requirement.
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| Range | Purpose |
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|:-------------------:|:-------------------------------------:|
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| `0x0000` - `0x00FF` | Trap Vector Table[^lc2-trap] |
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| `0x0100` - `0x2FFF` | Operating System[^matt-postiff-guide] |
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| `0x3000` - `0xCFFF` | Userspace |
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| `0xD000` - `0xFFFF` | Device Registers |
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[^lc2-trap]: {{< cite-ics edition="1" chapter="Appendix A.3 The Instruction Set" page="448" page-end="449" >}}
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[^matt-postiff-guide]: {{< cite-web
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author="Postiff, Matthew A."
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title="LC-2 Programmer's Reference and User Guide"
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site="University of Texas"
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url="https://www.cs.utexas.edu/~fussell/courses/cs310h/simulator/lc2.pdf"
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format="PDF"
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accessed="August 31, 2026"
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url-archived="https://web.archive.org/web/20251205052350/https://www.cs.utexas.edu/~fussell/courses/cs310h/simulator/lc2.pdf"
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url-archived-date="December 05, 2025"
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>}}
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## Stack
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The ISA does not define a stack as a distinct hardware structure, but it
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assumes one exists by convention. R6 is used as the stack pointer, and the
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stack is assumed to grow toward `0xFFFF`.
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This convention is not optional in practice: the `RTI` instruction relies on it
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directly. When an interrupt is serviced, the CC and PC are pushed onto the
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stack. `RTI` pops them back in reverse order to resume execution. Any deviation
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from the R6 convention would break interrupt handling.[^lc2-rti]
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[^lc2-rti]: {{< cite-ics edition="1" chapter="Appendix A.3 The Instruction Set" page="444" >}}
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## Memory-Mapped I/O
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LC-2 uses memory-mapped I/O: devices are accessed using the same load and store
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instructions used for regular memory, with no dedicated I/O instructions in the
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ISA.[^lc2-mmio]
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[^lc2-mmio]: {{< cite-ics edition="1" chapter="8.1.2 Memroy Mapped I/O Versus Special Input/Output Instructions" page="158" >}}
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The standard LC-2 operating system maps the following devices into the top of
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the address space. These are not defined by the ISA: they are the devices
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assumed by the reference implementation and its OS.
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| Address | Register | Description |
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|:--------:|:-------------------------------------------------------:|:------------------------------------------------------------------------------------------------------------------------|
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| `0xF3FC` | Video Status Register (`CRTSR`)[^lc2-devices-registers] | Bit 15, the ready bit, indicates whether the video device is ready to receive another character to print on the screen. |
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| `0xF3FD` | Horizontal Screen Position[^matt-postiff-guide] | Not implemented. |
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| `0xF3FE` | Vertical Screen Position | Not implemented. |
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| `0xF3FF` | Video Data Register (`CRTDR`) | A character written in the low byte of this register will be displayed on screen. |
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| `0xF400` | Keyboard Status Register (`KBSR`) | Bit 15, the ready bit, indicates whether the keyboard has received a new character. |
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| `0xF401` | Keyboard Data Register (`KBDR`) | The lower byte contain the last character typed on the keyboard. |
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| `0xFFFF` | Machine Control Register (`MCR`) | Bit 15 is the clock enable bit. When cleared, instruction processing stops because the clock signal stops pulsing. |
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[^lc2-devices-registers]: {{< cite-ics edition="1" chapter="Appendix A: The LC-2 ISA" page="430" >}}
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