Little Computer is an ISA, not a CPU
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Nicola Belluti 2025-01-22 15:36:12 +01:00
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[[main]] [[main]]
name = "CPU Documentation" name = "ISA Documentation"
pageRef = "/docs/introduction" pageRef = "/docs/introduction"
weight = 1 weight = 1

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<div class="hx-mt-6 hx-mb-6"> <div class="hx-mt-6 hx-mb-6">
{{< hextra/hero-headline >}} {{< hextra/hero-headline >}}
A complete toolset for the LC-2, <br> A complete toolset for the LC-2, <br>
LC-3 and LC-3b processors LC-3 and LC-3b ISAs
{{< /hextra/hero-headline >}} {{< /hextra/hero-headline >}}
</div> </div>
<div class="hx-mb-12"> <div class="hx-mb-12">
{{< hextra/hero-subtitle >}} {{< hextra/hero-subtitle >}}
A free and open-source emulator, assembler and compiler suite <br> A free and open-source emulator, assembler and compiler suite <br>
for the *Little Computer* series of CPU for the *Little Computer* series of ISAs
{{< /hextra/hero-subtitle >}} {{< /hextra/hero-subtitle >}}
</div> </div>
<div class="hx-mb-6"> <div class="hx-mb-6">
{{< hextra/hero-button text="Read the CPU docs" link="docs/introduction" >}} {{< hextra/hero-button text="Read the ISA docs" link="docs/introduction" >}}
</div> </div>

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weight = 100 weight = 100
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The *Little Computer* is a family of processors based on the Von Neumann The *Little Computer* is a family of *Instruction Set Architecture* (ISA) based
architecture, created by [Yale N. Patt](https://users.ece.utexas.edu/~patt/) on the Von Neumann architecture, created by [Yale N.
and [Sanjay J. Patel](https://sjp.ece.illinois.edu/) to teach their students Patt](https://users.ece.utexas.edu/~patt/) and [Sanjay J.
about computer architecture. Patel](https://sjp.ece.illinois.edu/) to teach their students about computer
architecture.
The processors in this family are extremely simple and they all feature a The processors in this family are extremely simple and they all feature a
*very* [RISC](https://en.wikipedia.org/wiki/RISC) instruction set; they all *very* [RISC](https://en.wikipedia.org/wiki/RISC) instruction set; they all
have a 16-bit address bus and a 16-bit data bus, except for the last CPU in the have a 16-bit address bus and a 16-bit data bus, except for the latest
family -- the LC-3b -- which has an 8-bit data bus. architecture of the group -- the LC-3b -- which has an 8-bit data bus.
The most famous CPU in this family is without a doubt the LC-3, the third The most famous ISA of this category is without a doubt the LC-3, the third
iteration of the architecture: on this processor people made a iteration of the architecture: on this specific ISA people made a
[subreddit](https://reddit.com/r/lc3), a [Wikipedia [subreddit](https://reddit.com/r/lc3), a [Wikipedia
page](https://en.wikipedia.org/wiki/Little_Computer_3), an [online page](https://en.wikipedia.org/wiki/Little_Computer_3), an [online
emulator](https://wchargin.com/lc3web/) and it's the easiest to find online emulator](https://wchargin.com/lc3web/) and it's the easiest to find online
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## Why am I doing this? ## Why am I doing this?
The goal of this project is to make more people know about this family of CPUs, The goal of this project is to make more people know about this family of ISAs,
which I believe is ideal for teaching computer architecture, operating systems which I believe is ideal for teaching computer architecture, operating systems
and programming languages. and programming languages.
Naturally, the focus will be on the last two processors of the series, the LC-3 Naturally, the focus will be on the last two ISAs of the series, the LC-3 and
and LC-3b, as they are the most recent, the most comprehensive, and, in my LC-3b, as they are the most recent, the most comprehensive, and, in my opinion,
opinion, the most interesting. the most interesting.
## Roadmap ## Roadmap