Added the base for LC-2 instructions page
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title = "Instructions"
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weight = 120
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+++
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{{% instruction
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mnemonic="ADD"
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short="Addition"
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formats=`ADD DR, SR1, SR2
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ADD DR, SR1, imm5`
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encoding="../imgs/add.drawio.png"
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encoding-dark="../imgs/add-dark.drawio.png"
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operation=`if (bit[5] == 0) {
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DR = SR1 + SR2;
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} else {
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DR = SR1 + SEXT(imm5);
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}
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setcc(DR);`
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examples=`ADD R2, R3, R4 ; R2 ← R3 + R4
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ADD R2, R3, #7 ; R2 ← R3 + 7`
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%}}
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If bit [5] is 0, the second-source operand is obtained from SR2. If bit [5] is
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1, the second-source operand is obtained by sign-extending the imm5 field to 16
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bits. In both cases, the second source operand is added to the contents of SR1,
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and the result stored in DR. The condition codes are set, based on whether the
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result is negative, zero, or positive.
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{{% /instruction %}}
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{{% instruction
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mnemonic="AND"
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short="Bitwise logical AND"
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formats=`AND DR, SR1, SR2
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AND DR, SR1, imm5`
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encoding="../imgs/and.drawio.png"
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encoding-dark="../imgs/and-dark.drawio.png"
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operation=`if (bit[5] == 0) {
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DR = SR1 & SR2;
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} else {
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DR = SR1 & SEXT(imm5);
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}
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setcc(DR);`
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examples=`AND R2, R3, R4 ; R2 ← R3 AND R4
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AND R2, R3, #7 ; R2 ← R3 AND 7`
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%}}
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If bit [5] is 0, the second-source operand is obtained from SR2. If bit [5] is
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1, the second-source operand is obtained by sign-extending the imm5 field to 16
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bits. In either case, the second-source operand and the contents of SR1 are
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bitwise ANDed, and the result stored in DR. The condition codes are set, based
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on whether the binary value produced, taken as a 2's complement integer, is
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negative, zero, or positive.
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{{% /instruction %}}
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{{% instruction
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mnemonic="BR"
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short="Conditional Branch"
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formats=`BR LABEL
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BRn LABEL
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BRz LABEL
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BRp LABEL
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BRnz LABEL
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BRnp LABEL
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BRzp LABEL
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BRnzp LABEL`
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encoding="../imgs/br.drawio.png"
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encoding-dark="../imgs/br-dark.drawio.png"
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operation=`if ((n && N) || (z && Z) || (p && P)) {
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PC = PC[15:9] @ pgoffset9;
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}`
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examples=`BRzp LOOP ; Branch to LOOP if the last result was zero or positive.`
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%}}
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Test the condition codes specified by the state of bits [11:9]. If bit [11] is
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set, test N; if bit [11] is clear, do not test N. If bit [10] is set, test Z,
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etc. If any of the condition codes tested is set, branch to the location
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specified by pgoffset9 on the same page as the branch instruction,
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{{% /instruction %}}
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{{% instruction
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mnemonic=`JMP / JSR`
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short=`Jump / Jump to Subroutine`
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formats=`JMP LABEL (L = 0)
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JSR LABEL (L = 1)`
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encoding="../imgs/jmp-jsr.drawio.png"
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encoding-dark="../imgs/jmp-jsr-dark.drawio.png"
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operation=`if (L == 1) {
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R7 = PC;
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}
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PC = PC[15:9] @ pgoffset9;`
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examples=`JMP FOO ; Jump to FOO.
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JSR FOO ; Jump to FOO, put return PC into R7.`
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%}}
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Unconditionally jump to the location specified by pgoffset9 on the same page as
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the JSR/JMP instruction. If the link bit L is set, the PC is saved in R7,
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enabling a subsequent return to the instruction physically following the JSR
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instruction.
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{{% /instruction %}}
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{{% instruction
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mnemonic=`JMPR / JSRR`
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short=`Jump, Base + Offset / Jump to Subroutine, Base + Offset`
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formats=`JMPR BaseR, index6 (L = 0)
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JSRR BaseR, index6 (L = 1)`
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encoding="../imgs/jmpr-jsrr.drawio.png"
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encoding-dark="../imgs/jmpr-jsrr-dark.drawio.png"
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operation=`if (L == 1) {
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R7 = PC;
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}
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PC = BaseR + ZEXT(index6);`
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examples=`JMPR R2, #10 ; Jump to R2 + #10.
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JSRR R2, #10 ; Jump to R2 + #10, put return PC into R7.`
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%}}
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Unconditionally jump to the location specified by adding ZEXT(index6) to the
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contents of the base register. If the link bit L is set, the PC is saved in R7,
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enabling a subsequent return to the instruction physically following the JSRR
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instruction.
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{{% /instruction %}}
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{{% instruction
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mnemonic="LD"
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short="Load Direct"
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formats=`LD DR, LABEL`
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encoding="../imgs/ld.drawio.png"
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encoding-dark="../imgs/ld-dark.drawio.png"
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operation=`DR = mem[PC[15:9] @ pgoffset9];
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setcc(DR);`
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examples=`LD R4, COUNT ; R4 ← mem[COUNT].`
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%}}
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Load the register specified by DR from the location specified by pgoffset9 on
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the same page as the LD instruction. The condition codes are set, based on
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whether the value loaded is negative, zero, or positive.
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{{% /instruction %}}
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{{% instruction
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mnemonic="LDI"
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short="Load Indirect"
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formats=`LDI DR, LABEL`
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encoding="../imgs/ldi.drawio.png"
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encoding-dark="../imgs/ldi-dark.drawio.png"
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operation=`DR = mem[mem[PC[15:9] @ pgoffset9]];
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setcc(DR);`
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examples=`LDI R4, POINTER ; R4 ← mem[mem[POINTER]].`
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%}}
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Load the register specified by DR as follows: Construct an address by
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concatenating the top seven bits of the program counter with the pgoffset9
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field of the LDI instruction. The contents of memory at that address is the
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address of the data to be loaded into DR. The condition codes are set, based on
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whether the value loaded is negative, zero, or positive.
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{{% /instruction %}}
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{{% instruction
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mnemonic="LDR"
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short="Load Base + Offset"
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formats=`LDR DR, BaseR, index6`
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encoding="../imgs/ldr.drawio.png"
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encoding-dark="../imgs/ldr-dark.drawio.png"
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operation=`DR = mem[BaseR + ZEXT(index6)];
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setcc(DR);`
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examples=`LDR R4, R2, #10 ; R4 ← contents of mem[R2 + #10].`
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%}}
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Load the register specified by DR from the location specified by a base
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register and index, as follows: The index is zero-extended to 16 bits and added
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to the contents of BaseR to form a memory address. The contents of memory at
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this address are loaded into DR. The condition codes are set, based on whether
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the value loaded is negative, zero, or positive.
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{{% /instruction %}}
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{{% instruction
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mnemonic="LEA"
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short="Load Effective Address"
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formats=`LEA DR, LABEL`
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encoding="../imgs/lea.drawio.png"
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encoding-dark="../imgs/lea-dark.drawio.png"
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operation=`DR = PC[15:9] @ pgoffset9;
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setcc(DR);`
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examples=`LEA R4, FOO ; R4 ← address of FOO.`
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%}}
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Load the register specified by DR with the address formed by concatenating the
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top seven bits of the program counter with the pgoffset9 field of the
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instruction. The condition codes are set, based on whether the value loaded is
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negative, zero, or positive.
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{{% /instruction %}}
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{{% instruction
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mnemonic="NOT"
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short="Bitwise Complement"
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formats=`NOT DR, SR`
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encoding="../imgs/not.drawio.png"
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encoding-dark="../imgs/not-dark.drawio.png"
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operation=`DR = ~SR;
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setcc(DR);`
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examples=`NOT R4, R2 ; R4 ← NOT(R2).`
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%}}
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Perform the bitwise complement operation on the contents of SR and place the
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result in DR. The condition codes are set.
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{{% /instruction %}}
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{{% instruction
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mnemonic="RET"
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short="Return from Subroutine"
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formats=`RET`
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encoding="../imgs/ret.drawio.png"
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encoding-dark="../imgs/ret-dark.drawio.png"
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operation=`PC = R7;`
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examples=`RET ; PC ← R7.`
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%}}
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Load the PC with the value in R7. This causes a return from a previous JSR or
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JSRR instruction.
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{{% /instruction %}}
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{{% instruction
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mnemonic="RTI"
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short="Return from Interrupt"
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formats=`RTI`
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encoding="../imgs/rti.drawio.png"
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encoding-dark="../imgs/rti-dark.drawio.png"
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operation=`NZP = mem[R6];
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R6 = R6 - 1;
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PC = mem[R6];
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R6 = R6 - 1;`
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examples=`RTI ; NZP, PC ← top two values popped off stack.`
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%}}
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Pop the top two elements off the stack; load them into NZP, PC.
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<h4>Notes</h4>
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On an external interrupt, the initiating sequence pushes the current PC onto
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the stack before loading the PC with the starting address of the service
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routine. The last instruction in the service routine is RTI, which returns
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control to the interrupted program by popping the stack and loading the value
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popped into the PC. (This instruction is included in this appendix for
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completeness. Its purpose and use are beyond the scope of what is normally
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covered in an introductory textbook.)
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{{% /instruction %}}
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{{% instruction
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mnemonic="ST"
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short="Store Direct"
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formats=`ST SR, LABEL`
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encoding="../imgs/st.drawio.png"
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encoding-dark="../imgs/st-dark.drawio.png"
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operation=`mem[PC[15:9] @ pgoffset9] = SR;`
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examples=`ST R4, COUNT ; mem[COUNT] ← R4.`
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%}}
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Store the contents of the register specified by SR into the memory location
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specified by pgoffset9 on the same page as the ST instruction.
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{{% /instruction %}}
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{{% instruction
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mnemonic="STI"
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short="Store Indirect"
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formats=`STI SR, LABEL`
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encoding="../imgs/sti.drawio.png"
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encoding-dark="../imgs/sti-dark.drawio.png"
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operation=`mem[mem[PC[15:9] @ pgoffset9]] = SR;`
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examples=`STI R4, POINTER ; mem[mem[POINTER]] ← R4.`
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%}}
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Store the contents of the register specified by SR into the memory location
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whose address is obtained as follows: Construct an address by concatenating the
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top seven bits of the program counter with the pgoffset9 field of the STI
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instruction. The contents of memory at that address is the address of the
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location to which the data in SR is to be stored.
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{{% /instruction %}}
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{{% instruction
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mnemonic="STR"
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short="Store Base+Offset"
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formats=`STR SR, BaseR, index6`
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encoding="../imgs/str.drawio.png"
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encoding-dark="../imgs/str-dark.drawio.png"
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operation=`mem[BaseR + ZEXT(index6)] = SR;`
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examples=`STR R4, R2, #10 ; mem[R2 + #10] ← R4.`
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%}}
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Store the contents of the register specified by SR into the memory location
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whose address is specified as follows: The six-bit offset is zero-extended to
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16 bits and added to the contents of BaseR to form a memory address. This is
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the address of the location into which the contents of SR is to be stored.
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{{% /instruction %}}
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{{% instruction
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mnemonic="TRAP"
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short="Operating System Call"
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formats=`TRAP trapvec8`
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encoding="../imgs/trap.drawio.png"
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encoding-dark="../imgs/trap-dark.drawio.png"
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operation=`R7 = PC;
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PC = mem[ZEXT(trapvect8)];`
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examples=`TRAP x23 ; Direct the operating system to execute the "IN" system call.`
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%}}
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Load the PC with the contents of the memory location obtained by zero-extending
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trapvec8 to 16 bits. This is the starting address of the system call
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specified by trapvec8. Load R7 with the PC, which enables a return to the
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instruction physically following the TRAP instruction in the original program
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after the service routine has completed.
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<h4>Notes</h4>
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Memory locations x0020 through x00FF, 192 in all, are available to contain
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starting addresses for system calls specified by their corresponding
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trap vectors. This region of memory is called the trap vector table. See Table
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A.3. Memory locations x0000 through x001F are not part of the trap vector
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table; therefore, x00 through x1F may not be used as trap vectors.
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{{% /instruction %}}
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