From 0fe878df7bca348fd12d3dd9b455a8e0cdc808c1 Mon Sep 17 00:00:00 2001 From: Nicola Belluti Date: Mon, 31 Aug 2026 16:25:35 +0200 Subject: [PATCH] Added more informations on LC-2 interrupts and startup --- content/isa-docs/lc-2/_index.md | 26 ++++++++++++++++++++------ content/isa-docs/lc-2/memory.md | 12 ++++++------ 2 files changed, 26 insertions(+), 12 deletions(-) diff --git a/content/isa-docs/lc-2/_index.md b/content/isa-docs/lc-2/_index.md index e9831dd..f2037d7 100644 --- a/content/isa-docs/lc-2/_index.md +++ b/content/isa-docs/lc-2/_index.md @@ -98,11 +98,25 @@ implicitly read by conditional branch instructions. [^lc2-condition-codes]: {{< cite-ics edition="1" chapter="5.1.7 Condition Codes" page="95" >}} +## Startup Behavior + +The ISA does not specify a default starting address or reset vector. Where the +PC is initialized when the processor powers on or resets is left entirely to +the implementation. {{< citation-needed >}} + ## Interrupt Support -LC-2 provides basic support for interrupts via the `RTI` (Return from -Interrupt) instruction. When an interrupt is serviced, the processor saves the -current status onto the stack and jumps to the interrupt handler. `RTI` -restores the PC from the stack when the handler returns. The ISA does not -specify the interrupt protocol, the bus signaling, or the acknowledgment -mechanism. These details are left to the implementation. +LC-2 provides support for vectored interrupts. When an interrupt is serviced, +the processor pushes the current PC and CC onto the stack, then reads an 8-bit +value from the interrupting device, called the interrupt vector (`INTV`). +`INTV` is zero-extended to 16 bits and used as a memory address into the +interrupt table: the value stored at that address is loaded into the PC, +transferring control to the interrupt handler.{{< citation-needed >}} + +The `RTI` (Return from Interrupt) instruction reverses this process, popping +the PC and CC from the stack to resume the interrupted +program.{{< citation-needed >}} + +Beyond this, the ISA does not specify the interrupt protocol in further detail: +the bus signaling and acknowledgment mechanism used to deliver `INTV` are left +to the implementation. diff --git a/content/isa-docs/lc-2/memory.md b/content/isa-docs/lc-2/memory.md index fee4cd9..13f0286 100644 --- a/content/isa-docs/lc-2/memory.md +++ b/content/isa-docs/lc-2/memory.md @@ -24,12 +24,12 @@ system, not the ISA itself. The ISA only defines the trap vector table at `0x0000 - 0x00FF`. Everything else, from the location of the OS to the boundary of userspace, is a software convention rather than a hardware requirement. -| Range | Purpose | -|:-------------------:|:-------------------------------------:| -| `0x0000` - `0x00FF` | Trap Vector Table[^lc2-trap] | -| `0x0100` - `0x2FFF` | Operating System[^matt-postiff-guide] | -| `0x3000` - `0xCFFF` | Userspace | -| `0xD000` - `0xFFFF` | Device Registers | +| Range | Purpose | +|:-------------------:|:--------------------------------------------------------------------------------------------------------------:| +| `0x0000` - `0x00FF` | Trap Vector Table[^lc2-trap] / [Interrupt Vector Table](http://localhost:1313/isa-docs/lc-2#interrupt-support) | +| `0x0100` - `0x2FFF` | Operating System[^matt-postiff-guide] | +| `0x3000` - `0xCFFF` | Userspace | +| `0xD000` - `0xFFFF` | Device Registers | [^lc2-trap]: {{< cite-ics edition="1" chapter="Appendix A.3 The Instruction Set" page="448" page-end="449" >}} [^matt-postiff-guide]: {{< cite-web